Thus, if this technique is coupled with the use of a sufficiently small nucleation area size, it is expected to enable the relaxation of the mismatched material without emission of misfit dislocations 15. We demonstrate in this paper that the epitaxial lateral overgrowth of GaAs on nano patterned Si substrates with dielectric films appears to be the most promising technique. Therefore, the direct epitaxial growth of III–V compounds on Si substrates remains the most desirable approach for III–V/Si hybrid integration. Nevertheless, such artificial GaAs/Si wafer organization is limited in size by the available III–V substrates, and as the donor GaAs wafer must be eliminated by etching, this technology is considerably more expensive than the epitaxial route 14. have obtained promising results with direct fusion bonding of GaAs on Si by successfully obtaining ohmic GaAs/Si highly conductive heterojunction through a 2 nm thick amorphous layer at the GaAs/Si interface 5. A promising technique which overcomes these problems is wafer bonding, which is a non-epitaxial method for III–V thin film integration on Si substrates and therefore not subject to the lattice matching limitations associated with epitaxial growth 13. This renders these layers inappropriate for applications involving carrier transport through the interfacial region. Moreover, even if these deposition procedures can keep the greater part of the epilayer free of defects, the relaxation process of GaAs on silicon leads to the presence of a high density of misfit dislocations located at the interface between Si and GaAs.
Significant improvements have been reported for many years, thanks to selective area epitaxy (SAE) of GaAs on Si substrates patterned with dielectric films 9, 10, 11, 12.
However, three major problems remain unresolved in GaAs layers grown directly on plain silicon substrates, i) the high density of threading dislocations due to the lattice mismatch with Si (around 4%), ii) the formation of anti-phase domains (APDs) due to the polar/non-polar semiconductor interface and iii) the formation of cracks due to the difference in thermal expansion coefficients of GaAs and Si 8. The first step toward this goal is to obtain high quality GaAs layer on a Si substrate, creating so-called virtual substrates. This epitaxial technique paves the way to hybrid III–V/Si devices that are free from lattice-matching restrictions, and where silicon not only behaves as a substrate but also as an active medium.Īlternative GaAs-on-Si substrates have a considerable market potential for replacing the costly GaAs substrate in producing traditional GaAs-based devices such as solar cells, photodetectors, LEDS, lasers, and microwave devices, and as a new technology for monolithic integration of GaAs elements and Si integrated circuits 1, 2, 3, 4, 5, 6, 7. With this method, we have experimentally demonstrated for the first time a monolithically integrated GaAs/Si diode with high current densities of 10 kA.cm −2 for a forward bias of 3.7 V. The nucleation from small width openings avoids the emission of misfit dislocations and the formation of antiphase domains. This method permits the integration of high quality and defect-free crystalline GaAs on Si substrate and provides active GaAs/Si heterojunctions with efficient carrier transport through the thin SiO 2 layer. Here we present an epitaxial technique based on the epitaxial lateral overgrowth of micrometer scale GaAs crystals on a thin SiO 2 layer from nanoscale Si seeds. But in spite of this effort, devices fabricated from them still use homo-epitaxy only. Interest in the heteroepitaxy of GaAs on Si has never failed in the last years due to the potential for monolithic integration of GaAs-based devices with Si integrated circuits.
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